The proposed solution is a new FPGA-based framework that allows to emulate a non-volatile architecture on any type of hardware. This framework can be used for debugging, and functional testing of logic. In addition, it can also be integrated into a yet-to-be-built computing system, so the
whole system can be tested as a whole. With this innovative solution, for the first time, rapid prototyping and validation can be performed on any battery-less hardware architecture.
Patent Status
PENDING
Patent Number
102020000022114, PCT/IT2021/050275
Priority Number
18/09/2020, 09/09/2021
License
INTERNATIONAL
Market
The growth of the Internet-of-Things (IoT) market has triggered the demand for programmable logic devices such as FPGAs, for controlling, connecting and processing applications across multiple industries.
According to some estimates, the global FPGA market in 2024 will grow by 45% compared to 2019. Furthermore, the IoT sector is also growing strongly, especially in the field of energy saving. Soon, there will be more than 75 billion devices.
For this reason, it is estimated that the green IoT sector with energy harvesting systems will be worth $ 468 million in 2021, reaching $ 701 million by 2026 (TOM).
The FPGA industry is critical to IoT development and is poised to steadily grow at 8% CAGR (SAM).
A reliable goal could be 10% of devices produced with our framework in the next decades (SOM).
Problem
With the growing number of IoT devices, arises the need to develop devices with very low energy consumption, that often works without using batteries but simple energy harvesters (temporary energy collectors such as capacitors).
The intermittency of power supply therefore becomes a factor that must be taken into consideration when developing the devices. Volatile memory elements are mounted on most of the devices currently on the market, which then lose their state with the power failure. Replacing the entire memory with a non-volatile type often has very high costs, so a good solution is to insert small non-volatile memories in the device architecture in order to save only some parameters necessary for the correct operation of the device.
For this reason, there is a need for a framework for prototyping and verifying the correct behavior of this new architecture.
Thanks to the innovative solution proposed, it is possible to have an advantage from an economic point of view (given that it is possible to develop architectures that only partially implement non-volatile memory), and from an environmental point of view. As the energy consumption of billions of devices would be optimized.
Current Technology Limits
The architecture of FPGAs and devices is not designed to emulate intermittent computational systems. This is because there are no specific commands in HDL to describe the different types of logic (volatile or non-volatile). The current FPGAs can implement both types of logic elements, but without the possibility of having a mixed system, in which volatile and non-volatile logic elements coexist.
This implies a low level of customization of the existing development platforms, with the consequent lack of optimization both from the economic point of view (since the non-volatile elements are more expensive), and from the environmental point of view (since their consumption is greater). For this reason, a new framework is needed to fill this gap.
Killer Application
This framework is completely polyvalent and can be used for almost all architectures. It can be used for the development, prototyping and functional verification of any architecture with a battery-less design, which needs non-volatile memories to implement transient computing.
For the enhancement of the project, it is sufficient to develop / adapt any architecture that requires non-volatile memories for transient computing and show the differences in terms of energy and economic savings.
Our Technology and Solution
This framework makes possible to quickly prototype and verify the correct functioning of different architectures that want to implement non-volatile logic and transient-computing. The framework can calculate the energy consumed by this logic, as well as implement various data saving policies. A voltage trace can be emulated that induces the device to continuous shutdowns (as in reality), and thanks to different thresholds that can be set, various behaviors can be set. In order to optimize the consumption of the architecture while maintaining high reliability and integrity of the data to be saved.
The framework will be integrated into existing FPGA-based development environments, in order to break down the barriers to accessing this technology as much as possible.
Advantages
This framework allows to reduce time and costs in designing and prototyping of systems that implement non-volatile architectures. It also offers the possibility of having estimates in terms of energy consumed by the new architecture, to understand which rescue policy is best suited to that application.
It is also the only solution currently on the market that allows you to have a development environment on FPGA that implements both volatile and non-volatile logic. This allows to correctly size the components to be used according to the needs, implying an energy saving, as well as an economic one.
Roadmap
The first 6 months would be dedicated to contacting FPGA manufacturers, to verify the possibility of entering into agreements. In addition, companies producing IoT devices would also be contacted, demonstrating the crucial benefit of using the framework, or in general of transient-computing with non-volatile logic architecture.
From the third to the ninth month, a commercial version of the framework would begin to be developed, which would be integrated with the existing toolchains and software environments of FPGA manufacturers.
Furthermore, from the sixth to the ninth month, we would dedicate ourselves to developing and adapting potential products with a transient architecture.
Months 9-12 would be dedicated to build and integrate the framework into their existing design processes.
TRL
Team
